The present invention relates to variation tolerant NoC systems.
Network-on-Chip (NoC) is an emerging paradigm for communications within large VLSI systems implemented on a single silicon chip. In a NoC system, modules such as processor cores, memories and specialized IP blocks exchange data using a network as a communication medium for the global information traffic. An NoC is constructed from multiple point-to-point data links interconnected by switches, such that messages can be relayed from any source module to any destination module over several links, by making routing decisions at the switches.
In a parallel trend, due to silicon technology scaling effects, boosting clock frequency of monolithic high-performance microprocessors has clearly reached a point of diminishing returns. As an effect, semiconductor devices are shifting towards massively parallel architectures with tens or even hundreds of cores integrated onto a single chip. With the increasing number of cores, scalability of communication architectures becomes critical for system performance and traditional bus architectures are not keeping up.
As transistor dimensions continue to shrink, it becomes harder and harder to precisely control the fabrication process. Transistors and wires become faster, but less predictable and, after fabrication, it is becoming more and more difficult to guarantee timing closure, and hence performance, across multiple copies of the chip. With traditional worst-case design techniques, the risk is to be too conservative or to discard too many chips, thus resulting in very low levels of yield. The emerging issue now is how to design differently than worst-case analysis.
Self-calibrating designs have been introduced as an alternative to worst-case characterization of silicon. Instead of relying on over-conservative worst-case assumptions, self-calibrating circuits tune their operating parameters to in-situ actual conditions. A run-time controller receives feedback from a checker that monitors correct operation of the circuit. When needed, circuit reliability can be restored at some power or performance cost, depending on actual silicon capabilities and noise conditions.
Self-calibrating links in the context of on-chip networks has been proposed where dynamic voltage swing scaling is used to dynamically adapt to environmental variations, design uncertainties, manufacturing parameter deviations or communication bandwidth requirements. While this transmission scheme adapts to variations of link physical parameters by discovering the real delay-voltage characteristic of the technology without any assumptions on it, there is no connection between link operating conditions and parameter variations affecting upstream or downstream functional units. In practice, self-calibrating links cannot prevent an upstream switch from violating its timing requirements due to delay variations.